This invention relates to a page printer, more particularly to a page printer with means for temporarily stopping direct memory access.
Page printers such as laser printers are widely used as output devices of computers, enabling small desktop publishing systems, for example, to produce text and graphics output with high quality and variety. A page printer prints a page by a scanning process in which a laser beam, for example, is switched on or off for each dot on the page, the number of dots being typically 300 per inch in both the horizontal and vertical directions. The switching is performed according to data comprising at least one bit for each dot on the page.
The operation of a page printer is controlled by a built-in microprocessor or similar central processing unit, hereinafter referred to as a CPU. A page printer also has various internal memories, such as a character pattern memory in which the dot patterns of characters are stored, and a frame or strip buffer memory in which the printer creates the dot pattern for an entire page, or a strip on the page. Since large amounts of dot data must be transferred between these memories, a page printer also has a direct memory access controller, hereinafter referred to as a DMAC, which is a device for transferring data to or from a memory at high speed without requiring intervention by the CPU.
The CPU, DMAC, and memories are interconnected by a bus over which data can be transferred a word at a time. (A word typically comprises 8, 16, or 32 bits.) During a direct memory access (hereinafter DMA) operation the bus is controlled by the DMAC and cannot be used by the CPU; that is, the CPU cannot operate.
Some scheme is necessary to ensure that the CPU will not be disabled for extended periods of time by long DMA operations, leaving it unable to deal with exigencies such as the arrival of new data from the computer. A typical scheme used in prior-art page printers is cycle stealing, in which the DMAC transfers data one word at a time, returning the bus to the CPU after each word.
Compared with the burst mode, in which the DMAC transfers data continuously, the cycle-stealing mode has many disadvantages. One is that, since CPU cycles are interspersed between the DMA cycles, a cycle-stealing DMA transfer takes longer to complete than a burst-mode DMA transfer. Another is that extra overhead cycles are required to transfer the bus right repeatedly between the CPU and DMAC. A third is that when CPU processing is contingent on the completion of the current DMA transfer, the CPU cycles inserted between the DMA cycles are wasted; during them the CPU does nothing but wait for the DMA transfer to end.